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| geometry process details principal device types cmlta94 cmpta94 cmpta92e cxta92 czta92 czta94 gross die per 5 inch wafer 25,214 process CP710V small signal transistor pnp - high voltage transistor chip process epitaxial planar die size 26 x 26 mils die thickness 7.1 mils base bonding pad area 6.1 x 4.9 mils emitter bonding pad area 5.2 x 5.2 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r0 (5-august 2010)
process CP710V typical electrical characteristics www.centralsemi.com r0 (5-august 2010) |
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